Physical Design Engineer
Core
Implement custom IP and SoC designs from RTL through GDSII, focusing on timing closure, power optimization, and physical verification for next-generation FPGA technologies.
Role type
Senior IC physical design engineer
Builds
Manufacturing-ready design databases for custom IP and SoC designs
Domain
Semiconductor / FPGA / Silicon Design Automation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL to GDSII implementation, synthesis, floorplanning, place and route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC, LVS, ERC, LEC), power integrity analysis, electromigration (EM), IR drop analysis, Tcl/Python/Perl/Shell scripting, EDA tool usage
Preferred skills
Advanced technology nodes (7nm, 5nm, 3nm), high-performance CPU/FPGA/AI accelerator/SoC design implementation, low-power implementation methodologies (UPF/CPF)
Technologies
Synopsys, Cadence, Siemens EDA, Tcl, Python, Perl, Shell
Responsibilities
Perform block-level physical design implementation from RTL through GDSII; Execute physical design flow stages including synthesis, floorplanning, power planning, place and route, CTS, and physical optimization; Perform static timing analysis and resolve timing violations; Support physical verification and signoff activities including DRC, LVS, ERC, LEC, IR drop, and EM; Analyze physical design results and implement corrective actions; Optimize implementations for performance, power, area, and reliability; Collaborate with RTL, Logic, DFT, CAD, and Architecture teams; Contribute to automation of physical design methodologies and flows.
Seniority
Senior, hands-on IC