Senior Principal Engineer (PE) / Subject Matter Expert (SME) – Quartus Timing Analysis & Optimization
Core
Architecting and developing next-generation Static Timing Analysis (STA), timing modeling, and optimization engines for the Quartus FPGA Compiler to ensure timing closure and scalability for large-scale digital designs.
Role type
Senior Principal Engineer / Subject Matter Expert (EDA Compiler)
Builds
High-performance timing analysis and optimization algorithms for FPGA compilation flows
Domain
Electronic Design Automation (EDA) / FPGA Physical Design
Deliverable
production ML models | product features
Required skills
Static Timing Analysis (STA), timing closure methodologies, timing modeling and correlation, physical design optimization, RTL-to-bitstream flows, Multi-corner multi-mode (MCMM) analysis, C++ development, large-scale optimization systems, placement and routing algorithms, clock analysis, path-based analysis, constraint management
Preferred skills
Quartus compiler experience, Path-based timing optimization, Clock-Reconvergence Pessimism Removal (CRPR), Latch-based timing analysis, Incremental optimization frameworks, Timing-driven placement and routing, Variation-aware analysis, multi-threaded/distributed EDA infrastructure, technical leadership via patents/publications
Technologies
C++, Quartus, FPGA
Responsibilities
Define technical roadmap for timing analysis and optimization, lead design of advanced timing engines, develop methodologies for timing convergence, partner with architecture teams for QoR improvement, architect next-generation STA capabilities, develop timing modeling methodologies, design scalable data structures and algorithms, provide technical mentorship and thought leadership
Seniority
Principal, hands-on IC with strategy & mentorship
