Static Timing Analysis (STA) Methodology Engineer
Core
Own timing across advanced-node, high-performance, low-power designs and lead the development of end-to-end STA methodologies and flows.
Role type
Senior Static Timing Analysis (STA) Methodology Engineer
Builds
Production STA flows, CAD utilities, and ML-assisted timing automation for high-performance AI chips.
Domain
Semiconductor design, advanced-node physical design, AI hardware
Deliverable
production ML models | infrastructure
Required skills
Static Timing Analysis (STA), PrimeTime (PT-SI, PTPX, PT-ECO), noise/crosstalk/OCV analysis, Tcl, Python, Perl, timing closure, signoff correlation, timing optimization, flow architecture
Preferred skills
ML-assisted timing automation, data-driven risk prediction, cross-functional leadership, EDA tool roadmap influence
Technologies
PrimeTime, Tcl, Python, Perl, RISC-V
Responsibilities
Lead cross-functional efforts to solve complex timing challenges across multiple IPs and technology nodes; Architect and optimize production STA flows to improve PPA and runtime efficiency; Develop and enhance STA methodologies from early estimation to post-route ECO; Design and maintain scalable CAD utilities and flow components; Partner with EDA vendors on advanced-node timing challenges.
Seniority
Senior, hands-on IC with technical leadership
