Senior Physical Design Engineer/Lead
Core
Backend implementation of FPGA/SoC devices from netlist to GDSII, optimizing performance, power, and area (PPA) for programmable logic structures and full-chip integration.
Role type
Senior Physical Design Engineer (FPGA/SoC backend)
Builds
FPGA and SoC chips for AI, cloud, networking, and edge markets
Domain
Semiconductor hardware design (ASIC/SoC) and FPGA technologies
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
floorplanning, power planning, placement, clock tree synthesis (CTS), routing, ECO implementation, timing closure, power integrity analysis, DRC/LVS/ERC verification, Tcl scripting, Python/Perl automation, low-power design methodologies, static timing analysis, physical verification flows, chip integration, bump planning, I/O budgeting
Preferred skills
advanced semiconductor process technologies (7nm/5nm), FPGA physical implementation flows, full-chip integration flows, AI/ML-assisted physical design optimization tools
Technologies
Synopsys IC Compiler II, Synopsys Fusion Compiler, Cadence Innovus, Cadence Encounter, Synopsys PrimeTime, Synopsys StarRC, Mentor Calibre, Synopsys DSO.ai, Fusion Compiler AI, Cadence Cerebrus
Responsibilities
Lead physical design implementation tasks from netlist to GDSII; Apply PPA optimization techniques across blocks or full-chip hierarchies; Collaborate with front-end design and architecture teams to meet constraints; Develop and improve physical design flows, methodologies, and automation frameworks; Participate in timing, power, EM/IR integrity, and sign-off verification; Integrate FPGA-specific physical design aspects like configurable logic block placement and fabric routing; Work with manufacturing partners to ensure manufacturability and yield targets; Debug physical design issues and drive tool enhancements; Mentor junior engineers and contribute to flow documentation.
Seniority
Senior, hands-on IC