Senior Physical Design Engineer
Core
Senior Physical Design Engineer responsible for chip-level implementation, timing closure, and low-power design using EDA tools.
Role type
Senior IC physical design engineer
Builds
High-performance AI hardware chips for edge-to-cloud computing
Domain
Semiconductor design / AI hardware
Deliverable
production ML models
Required skills
Physical design, timing closure, low-power design, EDA implementation, hierarchical floorplanning, EM/IR checks, power grid verification, scripting (TCL/Python), process concepts
Preferred skills
PDK management, foundry tapeout processes, physical design methodology and flow setup
Technologies
Cadence tools
Responsibilities
Perform top-level and block-level physical design, execute timing closure techniques, conduct low-power design and debugging, resolve EM/IR and power grid issues, automate tasks using TCL or Python scripts
Seniority
Senior, hands-on IC