Physical Design Engineer
Core
Implementing complex IC physical designs for next-generation chips to break through the memory wall and enable faster AI inference.
Role type
Physical Design Engineer (IC/SoC)
Builds
ASIC/SoC chips for AI accelerators and high-performance computing
Domain
Semiconductor hardware design, AI infrastructure
Deliverable
production ML models | product features
Required skills
floor planning, placement, clock tree synthesis (CTS), routing, sign-off, synthesis, static timing analysis (STA), power planning, IR drop analysis, DRC, LVS, DFT integration, EDA tool flows, scripting (TCL/Perl/Python), CMOS technology understanding
Preferred skills
experience with advanced technology nodes (7nm/5nm), timing closure, signal integrity, formal verification, high-performance computing (HPC) or networking chip experience, AI tool integration
Technologies
Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre
Responsibilities
Support physical implementation of ASIC/SoC designs from synthesis to sign-off; optimize performance, power, and area (PPA); ensure design rule check (DRC) and layout vs. schematic (LVS) compliance; collaborate with RTL and architecture teams on physical-aware design; develop automation flows in EDA tools.
Seniority
Mid-level IC engineer (2–5 years experience)