Design Engineer
Core
Physical design of high-speed CMOS ASICs for AI, cellular, networking, computing, and storage products, handling floor planning, routing, timing closure, and physical verification.
Role type
Senior IC physical design engineer
Builds
High-speed CMOS ASICs for industry-leading AI, cellular, networking, computing, and storage products
Domain
Semiconductor / ASIC Physical Design
Required skills
Floor planning, Routing, Timing analysis & closure, Physical verification, SerDes integration, Memory integration, I/O design, Standard-cell and custom block design, Power/area/performance tradeoffs, Signal integrity analysis, Debugging complex design issues
Preferred skills
Cross-functional collaboration, Independent work, Customer communication
Technologies
CMOS, SerDes, Standard-cell, Custom logic, High-speed ASICs
Responsibilities
Floor planning chips and blocks, Routing, Timing analysis (mission and test modes), Integration of memories, SerDes, and I/O, Physical verification to ensure error-free mask release, Debugging complex design issues during and after release
Seniority
Mid-level to Senior, hands-on IC
