Principal Engineer, Design Verification - DDR Memory Subsystems
Core
Technical leadership for verification of next-generation DDR memory subsystem IP integrated into Altera's FPGA products.
Role type
Principal Engineer, Design Verification
Builds
DDR memory controllers, PHYs, training logic, calibration flows, and memory subsystem integration for FPGA products
Domain
Semiconductor / FPGA / High-Speed Memory Interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, constrained-random verification, assertions (SVA), functional coverage, scoreboarding, protocol checking, regression automation, root-cause analysis, timing analysis, memory controller design, DDR PHY architectures, memory initialization and training sequences, calibration algorithms, AXI and AMBA interconnect protocols, cache coherency, high-performance memory interface verification, silicon validation, waveform analysis, protocol analyzers
Preferred skills
formal verification, emulation platforms, FPGA prototyping, post-silicon validation, Python, Perl, Tcl, Shell scripting, CI/CD pipelines, scalable regression frameworks, mentoring senior engineers
Technologies
SystemVerilog, UVM, SVA, DDR4, DDR5, LPDDR4, LPDDR5, HBM, HBM2, HBM3, AXI, AMBA
Responsibilities
Define and drive verification architecture, methodology, and strategy for DDR subsystems; Architect scalable UVM/SystemVerilog environments; Develop comprehensive verification plans with coverage and regression automation; Lead root-cause analysis of integration and timing issues; Mentor senior verification engineers; Drive continuous improvements in verification infrastructure and automation; Support post-silicon bring-up and characterization
Seniority
Principal, technical leadership and strategy
