Senior Staff Design Verification Engineer – Memory Sub-System (LPDDR/DDR/HBM )
Core
Design, verify, and deliver IP subsystem building blocks for high-speed memory interfaces (DDR, LPDDR, HBM) powering Marvell's custom chips for hyperscale cloud, AI, and data center customers.
Role type
Senior Staff IC Design Verification Engineer (Memory Sub-System)
Builds
Production-ready IP subsystems for PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, and Low-Speed IO
Domain
Semiconductor / Custom Compute and Storage / High-speed Memory Interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (IP subsystems)
Required skills
ASIC/SoC verification, System Verilog, UVM methodology, DDR/LPDDR/HBM protocols and architecture, debugging complex verification issues, digital design fundamentals
Preferred skills
JEDEC standards for DDR/LPDDR/HBM, assertion-based verification (SVA), performance modeling and traffic generation, emulation platforms (Palladium, Veloce), scripting (Python/Perl/Shell), low-power verification (UPF)
Technologies
System Verilog, UVM, Palladium, Veloce, Python, Perl, Shell, UPF
Responsibilities
Develop and execute verification plans for high-speed memory interfaces; Build and enhance UVM/System Verilog-based verification environments; Develop test benches, sequences, and checkers for functional and performance validation; Perform protocol-level verification for memory controllers and PHY interfaces; Analyze and debug simulation failures, identify root causes, and drive resolution; Contribute to coverage-driven verification (CDV) including functional, code, and assertion coverage
Seniority
Senior Staff, hands-on IC
