Design Engineer - Timing Methodology
Core
Develop and deploy advanced timing sign-off methodologies, modeling, and solutions for SOC and 3D/2.5D IC designs to ensure high yield and optimized margins.
Role type
Senior IC timing methodology engineer
Builds
Advanced timing sign-off flows and solutions for complex System-on-Chip (SOC) and 3D/2.5D integrated circuits
Domain
Semiconductor IC design, advanced silicon technologies, and production testability
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (timing sign-off flows and methodologies)
Required skills
Timing sign-off methodology development, SOC and 3D/2.5D IC design, statistical data analysis and modeling, silicon technologies, testability, yield optimization, Static Timing Analysis (STA) tools (Primetime, Tempus), flow automation scripting (TCL, Python, Perl, Unix shell), revision control, issue management, continuous integration/deployment
Preferred skills
Tapeout experience in high-volume/high-yield complex SOCs at advanced technology nodes, ability to work in fast-paced agile environments
Technologies
Primetime, Tempus, Innovus, TCL, Python, Perl, Unix shell
Responsibilities
Develop and deploy timing signoff methodologies for advanced technology nodes; Design and implement SOC, 3D/2.5D IC & multi-die signoff solutions; Participate & Lead in EDA flow development for Primetime, Tempus & Innovus
Seniority
Senior, hands-on IC
