Principal DFT Engineer
Core
Architect, implement, and validate innovative Design for Test (DFT) techniques on test-chips and hard-macros to prove Arm's soft IP power, performance, area, and functionality within a SoC context.
Role type
Principal DFT Engineer (IC)
Builds
DFT logic inserted into SoC designs, ATE-targeted test patterns, and silicon characterization solutions.
Domain
Semiconductor / SoC Design / Digital Logic
Required skills
Verilog RTL coding, TCL/Perl scripting, Unix/Linux proficiency, Scan compression/insertion, Memory BIST and repair, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics
Preferred skills
IEEE 1149/1500/1687/1838 standards, Synthesis & Static Timing Analysis, SoC multi-clock domain and low power design, Siemens DFT tools, Arm IP (Cortex CPUs, Mali GPUs, AMBA, CoreLink, CoreSight), 2.5D and 3D test
Technologies
Verilog, TCL, Perl, Unix/Linux, Siemens, Cadence, Synopsys DFT tools
Responsibilities
Insert DFT logic at RTL and Synthesis gate levels, collaborate with front-end design, verification, physical implementation, and test teams, generate test patterns for silicon validation, perform back-annotated gate level verification, and execute silicon debug and characterization.
Seniority
Principal, hands-on IC with mentorship responsibilities
