DFT Lead Engineer
Core
Leading DFT programs from chip-level specification through implementation, verification, and production release for Broadcom's ASIC designs.
Role type
Principal DFT Engineer
Builds
SoC DFT solutions including Scan, MBIST, TAP, LBIST, IO, and SerDes integration for 7nm and beyond
Domain
Semiconductor / ASIC Design / Digital & Analog Circuit Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (DFT integration and test vectors)
Required skills
DFT Architecture, ATPG, Scan Insertion, Scan Compression, Memory BIST, Boundary Scan, Verilog, Test-STA, IEEE1149.1/6, IEEE1687, IJTAG, ICL, PDL, Analog/Digital Circuit Design, Device Physics, Si Processing, Logical/Physical Synthesis, Transistor Reliability
Preferred skills
ATE experience, SerDes/DDR/PCIE/ENET/CXL IOBIST verification, Tessent SSN experience
Technologies
TCL, PERL, RUBY, PYTHON, C++, Verilog, DFT Compiler, Mentor TestKompress, TetraMax, Fastscan
Responsibilities
Define DFT specifications for ASICs, Implement DFT features (Scan, MBIST, TAP, LBIST, IO, SerDes), Collaborate with STA and DI Engineers for design closure, Generate and debug test vectors before tape release, Validate and debug test vectors on ATE during silicon bring-up, Assist with silicon failure analysis and yield improvement, Interface with global customer and engineering teams, Debug customer returned parts on ATE, Innovate DFT solutions for advanced nodes, Automate DFT and test vector generation flows
Seniority
Principal, hands-on IC with strategy & mentorship
