Memory Layout Design Engineer
Core
Designing high-quality memory layouts for advanced submicron FinFET processes (TSMC 5nm/3nm/2nm, Samsung) ensuring end-to-end deliverables within schedule.
Role type
Senior IC memory layout design engineer
Builds
Memory blocks and chip integration for SOC teams
Domain
Semiconductor manufacturing / Advanced node IC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Advanced submicron FinFET layout design, Cadence Virtuoso/Layout XL, Calibre/Hercules physical verification, memory architecture, floor-planning, hierarchy layout, signal/power routing, LVS/DRC/ERC/Antenna/Electro Migration analysis, team leadership, technical documentation
Preferred skills
Memory compilers, layout automation, SKILL programming, AI integration, new technology review leadership
Technologies
Virtuoso, Layout XL, Calibre, Hercules, SKILL
Responsibilities
Apply layout guidelines and process rules for high-quality designs, manage scheduling and floor-planning, ensure end-to-end deliverables, lead teams and train junior engineers, document layout methodologies and flows
Seniority
Senior, hands-on IC with mentorship responsibilities
