Staff Layout Engineer
Core
Designing and verifying physical layouts for memory, I/O, and standard cell circuits in advanced semiconductor processes.
Role type
Staff IC Layout Engineer
Builds
Memory, I/O, and standard cell libraries for chip manufacturing
Domain
Semiconductor / IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (Note: This is a hardware/IC role, mapping to 'physical' work in the context of chip fabrication)
Required skills
IC layout design, Cadence Virtuoso, CALIBRE verification, DRC/LVS/ERC/Antenna/Electro Migration checks, floor-planning, hierarchy layout, chip integration, memory topology knowledge, new process rule application
Preferred skills
Analog layout, memory compiler experience, SKILL/Script programming, team leadership, new technology review leadership
Technologies
Cadence Virtuoso (XL/VXL/EXL), CALIBRE, Hercules, 16nm/7nm/5nm/2nm/A14 processes
Responsibilities
Apply layout guidelines and process rules for quality designs, manage layout floor-planning and schedules, complete verification without supervision, lead or train junior engineers, compile layout methodology documentation
Seniority
Staff, hands-on IC with team leadership
