IC Layout Engineer
Core
Designing and verifying physical layouts for memory, I/O, and standard cell libraries in advanced semiconductor processes.
Role type
Senior IC Layout Engineer (Memory/Library Group)
Builds
Standard cell, memory, and I/O layout libraries for chip integration
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Cadence Virtuoso (XL/VXL/EXL), CALIBRE verification, DRC/LVS/ERC/Antenna/Electro Migration checks, submicron process knowledge (16nm to 2nm), floor-planning, hierarchy layout, memory topology, script programming (SKILL)
Preferred skills
Analog layout experience, memory compiler experience, SKILL programming, team leadership/training
Technologies
Cadence Virtuoso, CALIBRE, Hercules
Responsibilities
Apply layout guidelines and new process rules, schedule timelines and perform floor-planning, complete quality layout and verification independently, lead or train junior engineers, compile documentation for layout methodology and flow
Seniority
Senior, hands-on IC with team leadership capability