Sr Engineer/Layout Engineer, Memory CAD, Guadalajara
Core
Develop and maintain CAD software for memory product and process development, focusing on layout, verification, and automation workflows.
Role type
Senior IC Layout Engineer (Memory CAD)
Builds
Automation scripts, P-cells, and verification tools for physical design and tapeout
Domain
Semiconductor manufacturing / Memory (HBM, DRAM) / EDA
Deliverable
production ML models | product features | infrastructure
Required skills
Design Automation, analog layout, SKILL, Python, C/C++/Java/Perl/Lisp, Unix/shell scripting, PDK development, EDA tool flows
Preferred skills
VLSI circuit design, IC CAD tools (schematics/layout/simulation), CMOS implementation trade-offs, Machine Learning algorithms
Technologies
SKILL, Python, C, C++, Java, Visual Basic, Perl, Lisp, Unix, EDA tools
Responsibilities
Develop and support CAD software for product and process development; Build and validate P-cells, utilities, and automation scripts; Design automation for physical design and tapeout workflows; Collaborate with PI engineers on layout methodologies; Apply CMOS process fundamentals and design rules
Seniority
Senior, hands-on IC