Manager, Static Timing Analysis (STA)
Core
Lead a team responsible for timing closure and signoff of advanced FPGA designs to ensure high-performance, power-efficient silicon.
Role type
Manager, Static Timing Analysis (STA)
Builds
Next-generation FPGA platforms for AI, data center, and networking applications
Domain
Semiconductor / FPGA Design / Electronic Design Automation (EDA)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA) concepts, timing signoff tools (PrimeTime), synthesis and place & route flows, RTL design (Verilog/SystemVerilog), root-cause analysis of timing violations, team leadership, project execution
Preferred skills
FPGA architecture knowledge, advanced node design experience, scripting/automation (Tcl, Python), large-scale distributed engineering environments
Technologies
PrimeTime, Verilog, SystemVerilog, Tcl, Python
Responsibilities
Build, manage, and mentor a high-performing STA team; Own end-to-end STA for FPGA designs including constraint development and signoff; Define and implement robust STA methodologies and flows; Partner with RTL, synthesis, and physical design teams to resolve timing issues; Drive improvements in performance, power, and area (PPA); Ensure on-time delivery of timing closure milestones
Seniority
Manager, hands-on IC with leadership
