Senior Engineer
Core
Senior IC physical design engineer responsible for block-level floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification to meet congestion, timing, and area metrics.
Role type
Senior IC physical design engineer
Builds
Physical designs for integrated circuits
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Floor-planning, partitioning, placement, clock tree synthesis, routing, physical verification (LVS/DRC/ERC/Antenna), equivalence checks, static timing analysis (STA), crosstalk delay analysis, noise analysis, power optimization, ECO implementation, formal verification
Preferred skills
Experience with Innovus, Encounter, ICC, Caliber, LEC, Primetime
Responsibilities
Perform block-level floor-planning, partitioning, placement, clock tree synthesis, and routing; Execute physical verification including LVS, DRC, ERC, and Antenna checks; Conduct equivalence checks, STA, crosstalk, noise, and power optimization; Implement timing and functional ECOs; Resolve congestion and timing closure issues; Guide team members on physical design activities.
Seniority
Senior, hands-on IC