Lead ASIC Design Engineer
Core
Principal Digital Design Engineer serving as Chip Lead for next-generation silicon projects, responsible for top-level architecture, microarchitecture, and full chip integration.
Role type
Principal Digital Design Engineer (Chip Lead)
Builds
Next-generation ASIC/SoC chips
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features | infrastructure
Required skills
SystemVerilog/Verilog, RTL design, microarchitecture, front-end EDA tools (Synopsys/Cadence), timing constraints (SDC), Clock Domain Crossing (CDC), logic synthesis, Static Timing Analysis (STA), IP integration, silicon tape-out leadership
Preferred skills
Mixed-signal/PHY-adjacent architectures (SerDes, PCIe, DDR), DFT planning, scripting (Python, Tcl, Perl)
Technologies
SystemVerilog, Verilog, Design Compiler, Genus, PrimeTime, Tempus, SpyGlass, JasperGold
Responsibilities
Define top-level digital architecture and partition IP blocks; drive logic synthesis, STA, and CDC analysis; manage integration of analog macros and third-party IP; own tape-out sign-off and foundry handoff; mentor mid-level and junior engineers
Seniority
Principal, hands-on IC with strategic ownership
