IP Integration Engineer
Core
Developing die-to-die and die-to-memory PHY IP for large complex 2.5D and 3.5D ASICs, focusing on physical composition, integration methodologies, and optimization for high IO density.
Role type
Senior IC IP Integration Engineer (ASIC/PHY)
Builds
Custom silicon ASIC products for cloud computing AI engines, supercomputers, networking, and wireless solutions
Domain
Semiconductor / ASIC Design / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC design flow expertise (FET, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC), power/area/speed trade-off analysis, FinFET and GAA architecture knowledge, Cadence Innovus toolset, static timing report analysis (Tempus/Primetime)
Preferred skills
Cadence Virtuoso environment, RTL languages (SystemVerilog, Verilog, VHDL), scripting (Skill, TCL, Ruby, Bash, Perl, Python), Ansys Redhawk, AI tools (Chat GPT, Gemini, Cursor)
Technologies
Cadence Innovus, Cadence Virtuoso, Tempus, Primetime, Ansys Redhawk, SystemVerilog, Verilog, VHDL, Skill, TCL, Ruby, Bash, Perl, Python
Responsibilities
Develop detailed understanding of Broadcom's die-to-die PHYs; collaborate with cross-functional teams (analog, digital, physical composition, DFT, timing) to build PHYs; optimize size and power delivery for high IO density PHYs; analyze power integrity (droop, EM) in various use cases; develop/write PHY integration documentation; create checklist tasks for PHY IP integration; support customer and ASIC PHY integration questions
Seniority
Senior, hands-on IC
