3D Physical Design Engineer
Core
Design and analysis of 3D integrated products, combining traditional ASIC/SoC physical design with packaging, power, clock, and cooling analysis for AI chips.
Role type
Senior IC physical design engineer (3D integration)
Builds
3D integrated AI chips and novel 3D integration concepts
Domain
Semiconductor hardware / AI infrastructure
Deliverable
production ML models
Required skills
3D physical design, 3D die stacking, 3D chip design, die-to-die/wafer-to-wafer integration, full-chip physical verification, power/performance/area optimization, ICV/Calibre DRC/LVS resolution, IR/EM analysis, Tcl/Python scripting, RTL collaboration
Preferred skills
Full-chip floor planning, Synopsys tool suite, static timing analysis, clock distribution, cooling analysis
Technologies
ICV, Calibre, Alegro, Tcl, Python, Synopsys tool suite
Responsibilities
Perform block level and full-chip physical verification; optimize power/performance/area; resolve DRC and LVS issues; conduct IR/EM analysis; collaborate with architecture and RTL teams on 3D integration R&D
Seniority
Senior, hands-on IC
