Senior/Staff Silicon Physical Design Engineer
Core
Developing cutting-edge multi-core in-memory compute SoCs from RTL to GDS.
Role type
Senior/Staff Silicon Physical Design Engineer
Builds
Multi-core in-memory compute System on Chips (SoCs)
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models
Required skills
ASIC Physical Design (RTL to GDS), Synthesis, Floorplanning, Place and Route, Timing Analysis, Physical Verification, Clock Tree Synthesis (CTS), IP Integration, EDA Tools, Python Scripting, Tcl Scripting
Preferred skills
Top-level integration, Chip-package-board co-simulation, Semiconductor device physics, Multi-domain design
Technologies
Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Calibre, Redhawk
Responsibilities
Perform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification; Execute clock tree synthesis and custom clock-building techniques; Integrate IPs including memories, I/Os, embedded processors, DDR, and networking fabrics; Develop automation scripts in Python, Tcl, and Bash; Debug and solve technical challenges related to physical design.
Seniority
Senior/Staff, hands-on IC