R&D Engineer IC Design
Core
Designing cutting-edge CoWoS 2.5D/3D interposer designs for high-speed interfaces, including custom routing, bump map design, and physical verification for enterprise and mega-scale data center network switches.
Role type
IC Design Engineer (Advanced Packaging/Interposer)
Builds
Custom routing, bump maps, and interposer designs for high-speed interfaces
Domain
Semiconductor / Advanced Packaging / Data Center Networking
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
CoWoS/2.5D/3D interposer design, TSV design, micro-bumps, solder bumps, interconnect technologies, EDA tools (Cadence Innovus/Integrity, Synopsys 3DIC compiler, Mentor Calibre), high-speed signal integrity (SI), power integrity (PI), thermal analysis, semiconductor fabrication processes, scripting (Python, Tcl, SKILL)
Preferred skills
High-density interposer experience in complex packaging, automation of interposer design flow, 3DBlox interposer modelling language
Technologies
Cadence Innovus, Cadence Integrity, Synopsys 3DIC compiler, Mentor Calibre, Python, Tcl, SKILL, 3DBlox
Responsibilities
Design custom routing for high-speed interfaces, perform bump map design, execute routing and physical verification, interact with packaging/signal integrity/foundries to meet requirements, handle multiple interposer designs in parallel
Seniority
Senior, hands-on IC
