DFX Design Architect
Core
Define overarching strategy for Design for Test (DFT) and Design for Debug (DFD) to ensure world-class quality, minimize Test Cost, and accelerate Time-to-Market for next-generation FPGA and SoC families.
Role type
Senior IC DFX Design Architect
Builds
DFX architectures for multi-die (chiplet) systems, high-speed transceivers, and massive FPGA fabrics
Domain
Semiconductor / FPGA / ASIC / Hardware Testing
Deliverable
production ML models | product features | infrastructure
Required skills
Hierarchical DFT, Logic/Memory BIST, Scan Compression, Boundary Scan, JTAG/iJTAG, Silicon bring-up, Failure analysis, 2.5D/3D packaging, ASIL-D safety standards, EDA tool expertise (Tessent, DesignCompiler/DFTMAX), Tcl/Python scripting
Preferred skills
FPGA-specific testing (configuration RAM, programmable interconnect verification)
Technologies
IEEE 1149.1, IEEE 1149.6, IEEE 1500, IEEE 1687, IEEE 1838, Tessent, DesignCompiler, DFTMAX
Responsibilities
Define and document DFX architectures for multi-die systems and high-speed transceivers; Drive adoption of advanced DFX features like IJTAG and 3D-IC; Develop strategies to reduce Test Data Volume and Test Application Time; Lead definition of on-chip debug infrastructures; Partner with Silicon Design Architects to bake DFT/DFD features into hardware specifications; Influence EDA vendors to align roadmaps with architectural needs; Mentor senior and staff engineers at the Penang site
Seniority
Senior, hands-on IC with architectural leadership
