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DFT Design Engineer

San Jose, California, United States💼 Full-time💰 $149,100–$149,100🗓 2026-06-15 → 2026-07-31

Core

Designing and implementing DFT architectures and test flows for complex ICs including FPGAs, processors, DSPs, and multi-die packages to ensure manufacturability and quality.

Role type

DFT Design Engineer

Builds

FPGA, processor, DSP, SERDES, IO, and 2.5D/3D multi-die designs

Domain

Semiconductor IC Design / Programmable Logic

Deliverable

production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work

Required skills

DFT architecture definition, test logic insertion, ATPG pattern generation, RTL and gate-level DFT verification, EDA tool proficiency (synthesis, scan insertion, simulation, STA), scripting (Perl/TCL)

Preferred skills

Test compression, BIST (MBIST/LBIST), advanced fault models, 2.5D/3D multi-die design experience, high-speed IO/SerDes DFT

Technologies

Perl, TCL, ATPG tools, Synthesis tools, Scan insertion tools, Simulation tools, STA tools

Responsibilities

Define and implement DFT architectures and specifications; Perform test logic insertion and ATPG; Collaborate with IP and integration teams; Partner with test development for silicon bring-up and debug; Contribute to DFT methodology and automation flows; Ensure manufacturability goals (coverage, cost, yield)

Seniority

Senior, hands-on IC

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