Staff Formal Verification Engineer
Core
Own verification strategy and execution for complex out-of-order (OOO) processor blocks using formal verification techniques.
Role type
Staff Formal Verification Engineer
Builds
Formal verification environments and test plans for RISC-V processor blocks
Domain
Semiconductor / RISC-V Processor Design
Deliverable
production ML models
Required skills
Formal Verification, Out-of-Order Processor Architecture, Verification Strategy, RTL Debugging, Assertion Libraries, Scripting for Automation
Preferred skills
Chisel, Vector Execution Engines, Object-oriented Programming, VC Formal, JasperGold, VHDL, Verilog, SystemVerilog
Technologies
Chisel, VC Formal, JasperGold, VHDL, Verilog, SystemVerilog
Responsibilities
Identify blocks for formal verification, create formal test plans, implement/maintain FV environments in Chisel, apply FV techniques to prove correctness, debug RTL, guide/train team members, automate verification processes, review formal setups, maintain assertion libraries
Seniority
Staff, hands-on IC with mentorship
