Staff Engineer, CPU Core Verification
Core
Own CPU core-level verification for high-performance out-of-order RISC-V CPUs to ensure correct behavior in silicon.
Role type
Staff Engineer, CPU Core Verification
Builds
High-performance RISC-V CPU cores and clusters
Domain
Semiconductor / CPU Design / RISC-V
Deliverable
production ML models
Required skills
CPU verification, out-of-order microarchitecture, RTL, UVM, C/C++, assembly, waveform analysis, debug infrastructure
Preferred skills
Pre-silicon/emulation/post-silicon verification, coverage closure, cross-team collaboration
Technologies
UVM, C/C++, Assembly, RTL
Responsibilities
Plan and drive functional verification for CPU core features and complex microarchitectural scenarios; Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components; Debug simulation and emulation regressions using RTL understanding, waveforms, and logs; Build and enhance coverage models, testbenches, and debug infrastructure; Collaborate with design, validation, and test teams to support bring-up and delivery of robust CPU cores and clusters
Seniority
Staff, hands-on IC
