Interconnect Design Engineer
Core
Designing industry-leading CPU and interconnect IP (TileLink, cache controllers, protocol bridges) as highly-configurable generators using Chisel/Scala to accelerate RISC-V SOC adoption.
Role type
Junior IC hardware design engineer (CPU/Interconnect IP)
Builds
Customizable CPU and interconnect IP cores for RISC-V based SoCs
Domain
Semiconductor / CPU Architecture / Interconnect Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Cache/coherency architecture, NoC/interconnect fabrics, industry bus protocols (AXI, AHB, APB, CHI), functional programming, templated metaprogramming, compiler infrastructure, RTL design (Verilog/System Verilog/VHDL), TDD
Preferred skills
Scala/Chisel, Bluespec, RISC-V architecture, Git/Github/Jira/Confluence
Technologies
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, TileLink
Responsibilities
Architect and implement TileLink interconnects and cache controllers as RTL generators; implement self-configuring RTL generators; enhance designs for multi-core coherence; integrate designs into Chisel/FIRRTL framework; perform sandbox verification and collaborate on test plans; maintain documentation.
Seniority
Junior, hands-on IC
