Staff Engineer, Physical Design - High Speed Interconnects
Core
End-to-end physical design implementation of high-bandwidth Network-on-Chip (NoC) and Uncore subsystems, driving PPA outcomes by influencing RTL structures and floorplanning strategies.
Role type
Staff Physical Design Engineer (High-Speed Interconnects)
Builds
Scalable, high-frequency IP for next-generation compute platforms (RISC-V based)
Domain
Semiconductor / Chip Design / Physical Design
Required skills
Physical design flow execution (RTL-to-GDSII), Hierarchical floorplanning and macro placement, NoC architecture understanding, FinFET node implementation (7nm and below), EDA tool mastery (Synopsys/Cadence), Timing closure and routability, PPA tradeoff optimization
Preferred skills
Automated flow development, Technical mentorship, System-level data flow analysis
Technologies
Synopsys, Cadence, FinFET, NoC, RTL, GDSII
Responsibilities
Execute full physical design flow for complex NoC and Uncore subsystems; Partner with RTL/Architecture teams for early feasibility analysis and RTL restructuring; Define physical blueprints via hierarchical partitioning and macro placement; Solve unique NoC challenges like long-wire RC compensation and clock distribution; Develop automated flows for hierarchical implementation; Provide technical guidance to mid-level engineers
Seniority
Staff, hands-on IC with mentorship
