Staff Engineer, Physical Design - Caches
Core
Own the physical implementation of high-performance cache blocks and memory sub-systems from RTL to GDSII, acting as a bridge between architecture, RTL, and implementation teams to drive co-design optimizations.
Role type
Staff Physical Design Engineer (Caches/Memory Subsystems)
Builds
High-performance, dense, and power-efficient memory designs on advanced and legacy process nodes
Domain
Semiconductor chip design, specifically RISC-V compute platforms and memory subsystems
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical design implementation, Synthesis, Place & Route (PnR), Signoff, RTL reading, Memory architecture understanding, PPA optimization, Scripting
Preferred skills
Cross-abstraction layer co-design, Complex routing over macros, Critical path timing analysis, Dynamic/leakage power management
Technologies
Synopsys, Cadence
Responsibilities
Drive physical design implementation for cache blocks and memory sub-systems; Participate in Architecture/RTL/Implementation co-design; Solve memory-specific physical bottlenecks; Optimize block-level implementation for aggressive PPA goals; Collaborate with RTL designers, IP vendors, and power teams; Enhance physical design flows and automation scripts
Seniority
Staff, hands-on IC with cross-functional leadership
