Memory Layout Staff Engineer
Core
Develop full-custom memory layout and sign-off verification flows for high-performance analog circuits, specifically SRAM compiler blocks, ensuring physical verification closure and design rule compliance.
Role type
Staff Engineer, full-custom memory layout
Builds
High-performance SRAM compiler blocks and analog mixed-signal IPs for data infrastructure
Domain
Semiconductor, Analog Mixed-Signal (AMS), Advanced Process Nodes
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SRAM compiler layout, full-custom memory layout, physical verification (DRC, LVS, ERC, EM, IR drop), semiconductor process technologies, device physics, Cadence Virtuoso, scripting (Perl, Tcl, SKILL)
Preferred skills
Automation script development, mentorship, cross-functional collaboration
Responsibilities
Develop full-custom memory layout and sign-off verification flows; Collaborate with circuit designers to translate schematics into efficient layouts; Ensure physical verification closure by resolving DRC, LVS, ERC, and antenna violations; Lead layout reviews and mentor junior engineers; Develop automation scripts to enhance productivity
Seniority
Staff, hands-on IC with mentorship
