Lead Debug/Trace/Profiling Design Engineer
Core
Lead design of debug, trace, and profiling hardware IP for RISC-V processor cores to enable high-performance SOC designs.
Role type
Senior IC hardware design technical lead (debug/trace/profiling)
Builds
Customizable RISC-V processor subsystem IP with advanced debug, trace, and profiling capabilities (via careerplan.io/jobs/R-101025-lead-debugtraceprofiling-design-engineer-at-sifive)
Domain
Semiconductor / Chip Design / RISC-V Architecture
Required skills
Debug/trace/profiling architecture, JTAG/cJTAG interfaces, CPU architecture, SoC design, RTL design (Verilog/System Verilog/VHDL), Chisel/Scala, Object-oriented/functional programming
Preferred skills
RISC-V International Association engagement, Git/Jira/Confluence
Technologies
Chisel, Scala, FIRRTL, RISC-V, TileLink, JTAG, cJTAG, Verilog, System Verilog, VHDL
Responsibilities
Architect and implement debug/trace/profiling hardware, develop RTL generators for configurable design, integrate content into Chisel/FIRRTL framework, execute verification test plans, collaborate on microarchitecture exploration
Seniority
Senior, hands-on IC with leadership responsibilities
