Chip Design Engineer, Graviton Chip Design Team
Core
Define architecture and micro-architecture for a domain within a System-on-Chip (SoC) and write RTL code in Verilog for the AWS Graviton processor family.
Role type
Senior IC chip design engineer (SoC architecture & RTL)
Builds
AWS Graviton processors for Amazon EC2 cloud workloads
Domain
Semiconductor / Cloud Infrastructure
Deliverable
production ML models | product features
Required skills
SoC architecture definition, RTL design in Verilog, cross-functional collaboration, full lifecycle ownership
Preferred skills
IP integration, full design cycle (RTL/Verification/Synthesis/timing closure/CDC/Lint), Verilog/SystemVerilog, embedded processor systems, protocols (Ethernet, SATA, PCIe, DDR)
Technologies
Verilog, SystemVerilog, SoC, RTL, Ethernet, SATA, PCIe, DDR
Responsibilities
Define architecture and micro-architecture for a domain within an SoC, Write RTL code in Verilog, Support verification and emulation teams with test planning and debug, Collaborate with product definition, verification, software, and silicon integration teams
Seniority
Mid-Senior, hands-on IC
