Senior Chip Design Engineer, Nitro Chip Design Team
Core
Senior Chip Design Engineer owning critical IP blocks for AWS Nitro, guiding micro-architecture through RTL design, synthesis, timing closure, and tape-out.
Role type
Senior IC chip design engineer
Builds
Custom silicon for AWS Nitro (network and cloud management controller)
Domain
Semiconductor / Cloud Infrastructure
Deliverable
production ML models | product features
Required skills
Micro-architecture definition, RTL design (Verilog/System Verilog), Synthesis, Timing closure, Debug, Test plan development, Coverage review, Cross-functional collaboration
Preferred skills
Network-on-Chip (NOC) architecture, Coherent/non-coherent fabric design, SoC development cycle (Synthesis, STA, CDC, Lint), Design Automation tools, Protocol knowledge (AXI, CHI, DDR, Networking, PCIe)
Technologies
Verilog, System Verilog, C*, Perl, Python, TCL
Responsibilities
Define micro-architecture for assigned IP blocks, Code and debug RTL, Perform synthesis and timing closure, Ensure quality and reliability standards, Partner with Verification and Emulation teams, Collaborate with Product Definition, Software, and Physical Design teams
Seniority
Senior, hands-on IC
