Head - SoC Physical Design Manager
Core
Lead a highly skilled Physical Design organization to implement and signoff advanced integrated circuits, including complex mixed-signal SoCs, ensuring performance, power, area, and reliability objectives.
Role type
Senior IC Physical Design Manager (Mixed-Signal SoC)
Builds
Advanced integrated circuits and mixed-signal SoCs
Domain
Semiconductor / IC Physical Design
Required skills
Physical Design (Place & Route, STA, timing closure), Power Management (IR-drop, EM, power gating), Mixed-Signal Integration, Physical Verification (DRC, LVS), Team Leadership, EDA Methodology Development, Cross-organizational Collaboration
Preferred skills
Secure Product Physical Design, Analog/Digital Interface Design, Packaging Knowledge, Mentorship of Technical Leaders
Technologies
EDA tools for P&R, STA, Power Analysis, DRC/LVS, Mixed-Signal Design Flows
Responsibilities
Lead floorplanning, partitioning, placement, clock-tree implementation, routing, and physical optimization; Drive Static Timing Analysis and timing closure in multi-mode/multi-corner environments; Lead implementation and verification of power-management architectures; Ensure robust physical verification and signoff; Mentor engineers and develop future technical leaders; Establish and drive common methodologies and best practices across NXP; Collaborate with architecture and front-end teams to optimize designs early.
Seniority
Senior, hands-on IC leader with people management
