PDK Deck Developer
Core
Lead the Process Design Kit (PDK) Physical Verification (PV) team, driving development of verification decks, testing, and tool evaluations for advanced semiconductor technologies.
Role type
Senior IC PDK Physical Verification Team Lead
Builds
Calibre physical verification decks, PV tool flows, and infrastructure for CMOS, FinFET, bulk, SOI, RF, BiCMOS, and Power MOS technologies.
Domain
Semiconductor manufacturing / Physical Design Verification
Deliverable
production ML models
Required skills
PDK Physical Verification rule deck development, DRC/LVS/ERC/PERC/FILL deck creation, EMIR rule deck support, foundry process variation formats (ICT, IRCX), Calibre SVRF/TVF rule deck coding, Cadence PVS/Assura rule deck coding, PV tool validation, AI tool integration (LLM, Calibre AI, Virtuoso AI), cross-team alignment
Preferred skills
Perl, Python, Shell, C/C++, TCL programming, new tool/methods evaluation, automation of deck generation
Technologies
Calibre, CalibreXRC, Assura, Assura RF, Cadence PVS, Synopsys ICV, Virtuoso, Cadence QRC, StarRCXT, Voltus, Redhawk, Calibre AI, Virtuoso AI
Responsibilities
Manage and lead the PDK PV team, create Sciforma plans and release documents, drive PDK PV testing and customer support, refine PV specifications and planning, enhance PV productivity using AI tools, align on way of working across geographic teams, develop PV infrastructure and utilities, validate PV tools and flows, automate deck/techFiles generation
Seniority
Senior, hands-on IC
