Senior Design Engineer
Core
Senior STA Engineer responsible for complete static timing analysis (STA) signoff on complex System-on-Chips (SOCs), ensuring timing closure from architecture understanding through physical design flow.
Role type
Senior IC STA Engineer (SoC)
Builds
Complex SoCs with robust timing closure
Domain
Semiconductor / Digital IC Design
Required skills
Static Timing Analysis (STA), Timing constraints writing, Timing ECO flows, Physical design knowledge (Synthesis, Placement, CTS, Routing), Signal integrity analysis, Silicon debug, High-speed interface knowledge (DDR, SerDes, MIPI, USB), AI-enabled workflow automation
Preferred skills
Block/Subsystem/Top-level STA experience, High-speed IO timing exposure
Technologies
Industry standard Timing tools, AI agents/workflows
Responsibilities
Write and refine timing constraints for assigned blocks/subsystems/chip top, Collaborate with RTL, IP, Architecture, and Physical Design teams, Own complete STA closure from project start to signoff, Validate timing constraints and ensure signoff quality, Build AI-enabled workflows to improve execution efficiency, Analyze signal integrity reports and take corrective actions
Seniority
Senior, hands-on IC
