Senior Lead Engineer - STA
Core
Responsible for complete Static Timing Analysis (STA) signoff for System-on-Chip (SoC) or subsystems, including writing and refining timing constraints and ensuring SI closure.
Role type
Senior Lead Physical Design Engineer (STA)
Builds
SoC and subsystems ready for tapeout
Domain
Semiconductor physical design, advanced technology nodes (16nm, 5nm)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA), timing constraint writing, SDF generation and validation, Signal Integrity (SI) closure, physical design flows (placement, CTS, routing), AI integration in STA
Preferred skills
Experience with higher tech nodes (16nm, 5nm), leading capabilities in signoff function
Technologies
SDF, placement, CTS, routing, AI tools
Responsibilities
Write and validate timing constraints for SoC/subsystem design cycles, interact with Frontend, DFT, and IP functions, ensure complete timing signoff till tapeout, contribute to physical design problem solving and strategy definition per technology node
