Physical Design Engineer
Core
Implement advanced custom IP and SoC designs from RTL through GDSII, driving timing closure, power optimization, and physical verification for leading-edge semiconductor products.
Role type
Senior IC physical design engineer (SoC/FPGA)
Builds
Manufacturing-ready design databases for next-generation FPGA technologies
Domain
Semiconductor / FPGA / Custom Silicon
Required skills
RTL-to-GDSII implementation, static timing analysis (STA), floorplanning, place and route, clock tree synthesis (CTS), physical verification (DRC/LVS/ERC/LEC), power integrity analysis, IR drop analysis, electromigration (EM) analysis, PPA optimization, Tcl/Python/Perl/Shell scripting
Preferred skills
Advanced technology nodes (7nm/5nm/3nm), high-performance CPU/FPGA/AI accelerator design, low-power implementation methodologies (UPF/CPF)
Technologies
Synopsys/Cadence tools (implied by flow), Tcl, Python, Perl, Shell, UPF, CPF
Responsibilities
Perform full-chip and block-level physical design implementation, execute physical design flow stages (synthesis, floorplanning, CTS, place and route), resolve timing and signal integrity violations, develop and optimize clock and power distribution networks, conduct physical verification and signoff activities, analyze implementation results to drive corrective actions, optimize physical implementations for PPA and manufacturability, mentor junior engineers, contribute to physical design methodology automation
Seniority
Senior, hands-on IC (via careerplan.io/jobs/R02909-physical-design-engineer-at-altera)
