Staff Physical Design Engineer-DPG-LPDDR
Core
Lead end-to-end RTL-to-GDSII implementation for complex SoCs across advanced technology nodes, driving floor planning, power planning, CTS, place & route, and physical signoff.
Role type
Staff Physical Design Engineer (SoC)
Builds
World-class memory and storage solutions (DRAM, NAND, NOR) that transform data into intelligence.
Domain
Semiconductor / VLSI / Memory and Storage
Deliverable
production ML models
Required skills
Floor planning, CTS, P&R, STA, Low-Power Design, Physical Verification, Signoff, Tcl/Python/Perl/Shell scripting, AI/ML tools for design automation
Preferred skills
Custom layout design, Analog/mixed-signal integration, Generative AI and Agentic AI solutions adoption
Technologies
ICC2, Fusion Compiler, Innovus, PrimeTime, Calibre
Responsibilities
Lead end-to-end RTL-to-GDSII implementation; Drive floor planning, power planning, CTS, place & route, timing closure, and physical signoff; Own PPA optimization, low-power implementation, congestion management, and design convergence; Lead STA, SI, EM/IR, DRC, LVS, and reliability closure; Define physical design methodologies, automation strategies, and flow improvements; Partner with Architecture, RTL, DFT, Verification, CAD, and Product Engineering teams; Provide technical leadership and mentor engineers; Leverage AI tools to improve design productivity and quality.
Seniority
Staff, hands-on IC with technical leadership