Senior EDA Physical Design (PnR) Engineer
Core
Develop, deploy, and support advanced physical implementation methodologies for semiconductor designs, combining hands-on PnR expertise with EDA flow development and customer technical support.
Role type
Senior EDA Physical Design (PnR) Engineer
Builds
Production-quality RTL-to-GDSII implementation flows and reusable automation infrastructure for semiconductor SoCs
Domain
Semiconductor / EDA / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (EDA flows)
Required skills
Floorplanning, placement, clock tree synthesis, routing, timing closure, congestion mitigation, power/area optimization, Tcl/Python scripting, static timing analysis, SDC constraints, hierarchical SoC implementation, physical verification
Preferred skills
Advanced Tcl/Python/Perl scripting, physically-aware synthesis, multi-mode/multi-corner analysis, advanced-node implementation, flow standardization
Technologies
Synopsys Fusion Compiler, IC Compiler II, Cadence Innovus, Linux/Unix
Responsibilities
Perform physical implementation (floorplan, place, route, CTS, signoff); Develop and validate robust EDA flows and automation scripts; Evaluate new EDA tools and technologies via PoC; Provide hands-on technical support and training to semiconductor customers; Collaborate with R&D and product teams to resolve complex design issues.
Seniority
Senior, hands-on IC
