Lead Physical Design Engineer
Core
Execute block and chip-level physical design from synthesized netlist to GDSII for complex SoC/IP blocks in advanced technology nodes.
Role type
Senior IC physical design engineer
Builds
SoC and IP blocks
Domain
Semiconductor / VLSI
Required skills
Floorplanning, power grid design, placement and optimization, Clock Tree Synthesis (CTS), routing and post-route optimization, timing convergence, setup/hold timing closure, DRC/LVS signoff, IR drop and electromigration (EM) compliance, scripting for automation
Preferred skills
Cross-functional collaboration with RTL, DFT, and packaging teams, methodology improvements
Technologies
GDSII, MCMM, STA
Responsibilities
Execute floorplanning, placement, CTS, and routing; ensure timing and signoff closure; debug congestion and SI/crosstalk issues; collaborate with RTL, DFT, and packaging teams; contribute to automation scripts.
Seniority
Senior, hands-on IC
