Principal SoC Physical Implementation/STA Engineer
Core
Lead Static Timing Analysis (STA) for System-on-Chip (SoC) and block-level designs, ensuring timing closure across multiple modes and corners.
Role type
Principal SoC Physical Implementation/STA Engineer
Builds
Production SoCs and digital blocks meeting timing requirements for advanced technology nodes
Domain
Semiconductor / Digital IC Design / Physical Implementation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA), Synopsys Design Constraints (SDC), Multi-mode Multi-corner Multi-mode (MCMM) analysis, PVT variation analysis, Engineering Change Order (ECO) generation, RTL/Physical Design/DFT collaboration, EDA tool scripting and automation, team leadership
Preferred skills
Experience with false path and multicycle path handling, violation debugging (setup/hold/transition), cross-functional flow integration
Technologies
Synopsys Design Constraints (SDC), MCMM, PVT, EDA tools
Responsibilities
Create and validate SDC constraints for block and full-chip levels; Perform exhaustive timing analysis across multiple corners and modes; Debug and resolve setup, hold, transition, and path-based violations; Drive timing closure by generating and evaluating ECOs; Partner with RTL, physical design, and DFT teams; Develop and support implementation flows using EDA tools; Drive a team of STA engineers
Seniority
Principal, hands-on IC with team leadership
