Principle DFT Engineer
Core
Implementing and verifying scan architectures, performing scan insertion, generating and analyzing ATPG patterns, and executing Gate-Level Simulation (GLS) for complex SoC designs.
Role type
Senior IC DFT Engineer
Builds
Production silicon chips with high fault coverage
Domain
Semiconductor / Digital SoC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Scan Insertion, ATPG, Gate-Level Simulation (GLS), Verilog, SystemVerilog, DFT tool debugging
Preferred skills
Pre- and post-silicon test support
Technologies
Mentor/Siemens Tessent, Synopsys, Cadence
Responsibilities
Implement and verify scan architectures, perform scan insertion, generate and analyze ATPG patterns for stuck-at and transition faults, execute GLS with and without SDF for DFT validation, collaborate with RTL, physical design, and test teams to ensure clean DFT signoff
Seniority
Senior, hands-on IC
