Senior IP Verification Engineer
Core
Pre-silicon verification of complex IPs and subsystems involving RISC-V CPU cores, memory controllers, and interconnects.
Role type
Senior IC IP verification engineer
Builds
Verified IP modules and subsystems for integration into SoCs
Domain
Semiconductor hardware design, RISC-V architecture, memory systems
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production verification environments and test cases
Required skills
UVM methodology, RISC-V architecture, memory controller design, interconnect protocols (AHB/AMBA), System Verilog, C/C++, directed and constrained random verification, functional and code coverage analysis, formal verification, assertion-based verification, pre- and post-silicon debugging
Preferred skills
Perl, TCL, Python scripting
Technologies
UVM, System Verilog, Verilog, C/C++, Perl, TCL, Python, AHB, AMBA, DDR3/4, LPDDR, FPGA, Emulation platforms
Responsibilities
Define and write IP verification plans based on requirements; architect, develop, debug, and run UVM-based verification environments for RTL simulation; create stimulus and assertions; execute verification plans and run regressions; analyze code and functional coverage; interface with HW, FW, SW, and architecture teams; debug designs in simulation and on the bench.
Seniority
Senior, hands-on IC
