Principal DFT Engineer
Core
Architect, implement, and validate in-vehicle networking devices and DFT features for automotive-grade SoC products.
Role type
Principal Hardware DFT Engineer
Builds
Automotive-grade System-on-Chip (SoC) designs with advanced test strategies
Domain
Semiconductor / Automotive Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Scan architecture design, ATPG (Automatic Test Pattern Generation), Memory BIST (MBIST), Logic BIST (LBIST), Boundary Scan & JTAG, Test compression, Verilog/SystemVerilog, Static Timing Analysis (STA), SDC constraints, Gate-level simulation (GLS), ATE data analysis, Tcl/Python/Perl scripting
Preferred skills
Experience with Synopsys TestMAX/DFT Compiler, Mentor Graphics Tessent, Cadence Modus
Technologies
Synopsys, Mentor Graphics (Tessent), Cadence, Verilog, SystemVerilog, Tcl, Python, Perl
Responsibilities
Define and implement advanced DFT strategies including scan insertion and BIST; Lead integration of digital subsystems and generate ATPG patterns; Drive post-silicon validation and debug activities; Coordinate with physical design teams for timing closure and test pattern operational readiness
Seniority
Principal, hands-on IC
