Senior/Staff Digital Design Engineer
Core
Architecting, designing, and integrating PHY IP blocks for high-speed interfaces within SoCs.
Role type
Senior/Staff Digital Design Engineer (SerDes/High-Speed IP)
Builds
PHY IP blocks for Ethernet SerDes, USB, PCIe, HDMI, DisplayPort, MPHY, and CPHY
Domain
Semiconductor / SoC Design / High-Speed Interfaces
Required skills
PHY IP architecture, RTL design, SoC integration, cross-functional collaboration
Technologies
SerDes, Ethernet, USB, PCIe, HDMI, DisplayPort, MPHY, CPHY
Responsibilities
Architect PHY IPs for high-speed interfaces; Develop RTL code for PHY IPs; Integrate PHY IPs in front-end and back-end flows; Collaborate with MAC, DV, and analog teams for system-level verification and co-simulation.
Seniority
Senior/Staff, hands-on IC
