Staff Engineer, HIG HBM Layout
Core
Design and development of critical analog, mixed-signal, and custom digital blocks with full chip-level integration support for High Bandwidth Memory (HBM) used in AI and high-performance computing.
Role type
Staff IC Layout Design Engineer
Builds
Custom analog/mixed-signal blocks and full chip layouts for HBM
Domain
Semiconductor / VLSI / Memory
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout design, Mixed-signal layout, Custom digital block design, Full chip integration, LVS/DRC/Antenna verification, Cadence VLE/VXL, Mentor Calibre DRC/LVS, Temperature sensor design, PLL design, ADC/DAC design, LDO design, Bandgap reference design, Charge pump design, Current mirror design, Comparator design, Differential amplifier design, Analog layout fundamentals (matching, electromigration, latch-up, coupling, crosstalk, IR-drop), Layout effects on circuit performance (speed, capacitance, power, area), Design hierarchy understanding, Memory architecture understanding, Physical verification
Preferred skills
Multiple tape-out support, Managing multiple layout projects
Technologies
Cadence VLE, Cadence VXL, Mentor Calibre
Responsibilities
Design and develop critical analog, mixed-signal, and custom digital blocks; Perform layout verification (LVS/DRC/Antenna) and quality checks; Guide junior team members in sub-block-level layout execution; Lead planning, scheduling, and delegation for project milestones; Collaborate with global engineering teams
Seniority
Staff, hands-on IC with leadership
