Design Verification Engineer
Core
Own and execute functional verification for block-level and full-chip designs from specification through tape-out for advanced DRAM and emerging memory architectures.
Role type
Senior IC design verification engineer (SystemVerilog/UVM)
Builds
Production memory and storage products (DRAM, NAND, NOR) for data centers, AI, 5G, and mobile applications
Domain
Semiconductor manufacturing (Memory/Storage)
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, constrained-random simulation, directed simulation, RTL debugging, coverage closure (functional/code/assertion), specification analysis, testbench architecture
Preferred skills
Mentorship of junior engineers, verification flow development, AI tool integration for verification
Technologies
SystemVerilog, UVM, simulation environments, verification tools
Responsibilities
Develop and maintain verification plans, test strategies, and coverage models; Architect and maintain SystemVerilog/UVM-based testbenches; Run simulations and debug functional failures; Drive coverage closure; Collaborate with design engineers to resolve RTL issues; Provide verification status updates and risk assessments; Contribute to verification tool and flow development; Mentor junior engineers
Seniority
Senior, hands-on IC with mentorship responsibilities
