Design Verification Engineer
Core
Own and execute functional verification for block-level and full-chip designs from specification through tape-out for advanced DRAM and emerging memory products.
Role type
Senior IC design verification engineer
Builds
Production DRAM and emerging memory chips
Domain
Semiconductor / Memory / SystemVerilog
Required skills
SystemVerilog, UVM, constrained-random simulation, directed simulation, RTL debugging, coverage closure, specification analysis, testbench architecture
Preferred skills
Mentorship, verification flow development, AI tool usage for verification
Technologies
SystemVerilog, UVM, DRAM architectures
Responsibilities
Develop and maintain SystemVerilog/UVM testbenches, execute simulations, drive coverage closure, debug functional failures, collaborate with design engineers, mentor junior engineers, contribute to verification methodology
Seniority
Senior, hands-on IC
