Senior Engineer - Design Verification
Core
Develop and maintain verification activities for DRAM design, focusing on accelerating verification cycles and improving debug efficiency using AI-based tools and automation frameworks.
Role type
Senior IC design verification engineer (DRAM)
Builds
Pre-silicon block level and full chip designs for DRAM and emerging memory architectures
Domain
Semiconductor / Memory / Digital & Mixed Signal Verification
Deliverable
production ML models | product features
Required skills
UVM, SystemVerilog (SV), Test bench development, Test case generation, Simulation analysis, Debugging, Perl scripting, Python scripting, Digital circuit understanding, Mixed signal circuit understanding
Preferred skills
Experience with Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice, Micron-specific simulators, Agentic AI Flow integration
Technologies
UVM, SystemVerilog, Perl, Python, Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice
Responsibilities
Assist with overall verification activities of DRAM design, Develop and maintain test benches/test vectors using simulation tools, Run regressions for coverage analysis and improvements, Collaborate with CAD, EDA, and software teams to integrate AI-driven flows
Seniority
Senior, hands-on IC
